Increased integration of semiconductor memory devices may be obtained by decreasing the minimum critical dimensions of the device features. However, the extent to which feature dimensions can be reduced can be limited by process overlay margins, which are related to the need to prevent the creation of a pattern bridge (i.e., electrical connections) between layers. For example, in a 90-nanometer dynamic random access memory (DRAM), at least 30-nanometer misalignment margins are sometimes required on a critical layer. Accordingly, improvement in process margins may allow increased integration of memory devices.
With a sharp decrease in the minimum critical dimension of semiconductor capacitor devices that have storage nodes stacked over bit lines, the need for improvement in their process margins may be particularly important. When storage nodes are formed over bit lines, the storage nodes should be electrically connected to a semiconductor substrate thereunder to operate a capacitor. For example, an interconnection structure may connect the storage nodes to the semiconductor substrate. The interconnection structure may use buried contacts (BC), and BC pads under the BC to connect the storage nodes to the semiconductor substrate.
However, as the minimum critical dimension of the semiconductor memory device decreases, it may become difficult to reliably obtain a process margin for forming the interconnection structure. As a result, the interconnection structure may not be completely insulated from a bit line interconnection structure, which connects bit lines to the semiconductor substrate. The bit lines have a structure in which a contact for the connection to the bit lines, e.g., a direct contact, is connected to a direct contact pad thereunder. However, a sharp decrease in the minimum critical dimension may cause the BC to not be completely insulated from the direct contact pad, which may render the storage node inoperable.
FIG. 1 is a cross-sectional view of a semiconductor device having conventional storage nodes. Referring to FIG. 1, capacitor storage nodes 60 are formed over a semiconductor substrate 10 so as to be electrically connected to the semiconductor substrate 10. The storage nodes 60 are positioned over bit lines 51 and 52 and are cylindrical so as to secure a wider effective area of a capacitor.
The storage nodes 60 are electrically connected to an active region 11 of the semiconductor substrate 10 via buried contact pads 41 penetrating through first dielectric layers 31 and buried contacts 61 penetrating through second dielectric layers 35. An isolation region 15 defines the active region 11 in the semiconductor substrate 10.
The buried contacts 61 penetrate through the second dielectric layer 35 in plug form passing apart from the bit lines 51 and 52. A capping isolation layer 56 is formed on the bit lines 51 and 52 and a spacer 57 is formed on the sidewalls of the bit lines 51 and 52 so that the bit lines 51 and 52 are isolated from the buried contacts 61. The buried contact pads 41 are connected to the semiconductor substrate 10, passing between gates 22 and 23. Capping dielectric layers 26 are formed on the gates 22 and 23 and spacers 27 are formed on the sidewalls of the gates 22 and 23 so that the gates 22 and 23 are insulated from the buried contact pads 41. The bit lines 51 and 52 are electrically connected to the semiconductor substrate 10 via a direct contact 55 penetrating through a second dielectric layer 35 and a direct contact pad 45 penetrating the first dielectric layer 31.
However, as the minimum critical dimensions of semiconductor devices get smaller, an overlay margin or a misalignment margin between layers is reduced. Accordingly, it may be difficult to obtain the necessary process margins. For example, in area A of FIG. 1, if a small misalignment occurs in a state of a small process margin, one of the buried contacts 61 may lie very close to the direct contact pad 45 for the bit lines 51 and 52. As a result, in area A, a pattern bridge, or an electrical bridge, may be created between the direct contact pad 45 and one of the buried contacts 61.
Accordingly, to avoid a pattern bridge, or electrical bridge, a sufficient process margin or an alignment margin should be obtained between the direction contact pad 45 and one of the buried contacts 61. However, if the sizes of the buried contacts 61 are reduced in an attempt to obtain the alignment margin, their contact resistance may increase unacceptably and may deteriorate performance of the semiconductor device. Accordingly, limitations may exist to reducing the sizes of the buried contacts 61 to obtain alignment margins.
A pattern bridge or electrical bridge may also hinder an attempt to change the arrangement of the storage nodes 60. Currently, the storage nodes 60 extend and are repeated in a longitudinal direction. However, as the minimum critical dimension of a semiconductor device decreases, a gap between nodes 60 may become insufficient, and a pattern bridge or electrical bridge may occur between the storage nodes 60.